Microsemi Corporation Senior Physical Design Engineer (Place & Route) in Bayan Baru, Malaysia


  • Own macro level and potentially system level functional modules and implement the macros to high quality standard
  • Develop and implement floor-planning, physical design flows, Place & Route and close timing on very large and complex ASICs and SOCs in Very-Deep Sub-Micron (VDSM) process technology nodes.
  • Work closely with the Synthesis, DFT and various teams across the world to deliver blocks in hierarchical chips for tapeout in a timely, high quality and cost-effective manner.
  • Implement Low Power physical design flows and methodologies such as Power-Gating, Clock-Gating and MBR flows.
  • Power distribution planning; Placement and optimization (timing/area/power); Clock network planning; Clock tree synthesis/balancing; Post-route timing optimization and Timing/Signal Integrity analysis, Power Analysis.
  • Potentially drive multiple blocks in parallel towards P&R/STA/DRC-LVS and IR Drop closure.
  • Enhance tools, flows and methodologies to meet design TAT
  • Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule.


This position requires at least BSEE with 5-7 years of ASIC development experience in a fast paced environment. You are required to have expertise in a wide range of areas in design, tools and flows:

  • BEng/MEng in EE or equivalent with the completion of several complexes ASIC or IC tapeouts in VDSM process technology nodes.
  • Experience taking large blocks to timing, physical design and DRC/LVS closure.
  • Experience in physical design with the understanding of VDSM effects and issues with excellent debugging and analytical skills.
  • Understand floor planning, placement and optimization for timing closure, clock network planning, power distribution planning and routing.
  • Experienced in main P&R tools such as Synopsys ICC/PT, Cadence Innovus and ETS.
  • Post layout physical verification and DFM rules (Cadence PVS).
  • Understand Low Power methodology, Static Timing Analysis, Signal/Power Integrity to meet design goals.
  • Experienced in scripting (TCL, PERL & Shell) and working knowledge of HDL (Verilog, VHDL) with solid understanding of UNIX/LINUX.
  • Knowledge of synthesis tools (e.g. Design compiler, Genus or equivalent) and static timing analysis tools (e.g. Prime Time or equivalent) is a plus.
  • Good verbal and written communication skills. Strong interpersonal skills.
  • Ability to lead and mentor others and work under challenging environment

Equal Opportunity Employer Minorities/Women/Protected Veterans/Disabled