Microsemi Corporation Staff Engineer, CAD in Bayan Baru, Malaysia

Our global growth continues, and we want you to be a part of it.

Microsemi is currently looking for a Staff Engineer to join our Advanced Engineering Services Division as a Staff Digital CAD Engineer in Penang, Malaysia.

Duties & Responsibilities:

As a member of the Design Methodology team you will develop flows and methodologies that optimize results in the realms of synthesis, test, physical design, and static timing analysis. Tasks involved would be:

  • Development and implementation of scripts that automate the usage of tools used in the digital CAD flow; in particular: digital logic simulation, synthesis, static timing, physical design and physical verification

  • Library creation of digital logic standard cells and RAMs in CMOS and FinFET technologies

  • Support of the flow and tools, as described above, by interacting with the engineers in the Product Development Group; this includes the creation and delivery of training to educate users, as well as assisting users as they use CAD tools and methods


  • Bachelor's or Master's Degree in Electrical Engineering or Computer Engineering
  • 5 or more years of industry experience in digital design, DFT, physical design, or CAD flow development
  • Excellent analytical and debugging skills and the ability to proactively solve issues
  • Proven ability to thrive on, learn and adapt to new methodologies and technologies
  • Ability to function and thrive in a team environment as well as an individual contributor
  • Ability to work with multi-site teams
  • Excellent verbal and written communication skills in English
  • Excellent documentation skills
  • Solid understanding of UNIX/Linux
  • Strong scripting and programming skills
  • Experience using Verilog/VHDL, Tcl/Perl
  • Knowledge of RTL coding practices for optimal synthesis and DFT results
  • Knowledge of digital simulation
  • Knowledge of synthesis and static timing
  • Understanding of defect mechanism in deep submicron technologies, and different fault models used to represent them
  • Knowledge of Built-In-Self-Test (BIST) for RAMs
  • Knowledge of low power methodologies and impact on overall design goals
  • Knowledge of JTAG IEEE standard to test board level connections
  • Experience the following in any of the following tools would be an asset: Cadence NC Sim, Genus, Innovus, Tempus, or Synopsys Design Compiler, DFT Compiler, TetraMax, PrimeTime ;
  • Experience with designs at 28nm and lower technologies (an asset)

Skills that are would be an asset:

  • Knowledge of transistor level simulation tools (SPICE)

Equal Opportunity Employer Minorities/Women/Protected Veterans/Disabled