Microsemi Corporation Mixed-Signal Digital Design Staff Engineer in Bayan Baru, Malaysia

The Mixed Signal Development Group (MSDG) is responsible for delivering analog and mixed-signal IP to divisions within Microsemi. We work with leading edge CMOS processes to produce analog integrated circuits for wireline and RF applications. From T1/E1 to DDR to 56Gb/s SERDES, we enable technology that allows Microsemi's products to interface to the outside world.

As a member of the Mixed-Signal Development Group, the candidate will be supervised by a team manager and be engaged in the design and verification of PLLs, high speed SERDES, integrated filters, ADCs, DACs, and other analog building blocks.

The digital content of this IP is increasing as we move to 28nm and smaller geometries. Senior/Staff level candidates are required to manage and deliver this digital content. Some of the tasks will include: specification/design/verification of digital blocks, co-design of mixed-signal blocks with internal analog design team, co-design of DSP blocks with internal DSP team, and development of DDR interfaces. Assisting with the integration of externally purchased IP will also be required.

The Mixed Signal Development Group looking to grow our design group within Microsemi's Penang facilities. We are seeking an individual with both design and verification experience to expand this group.

Responsibilities:

  • Read and understand engineering documents for digital blocks and mixed-signal systems.
  • Architecture and RTL coding of high-speed digital circuits, modeling of analog blocks.
  • Developing Testbenches and Verification Components such as UVCs, models, BFMs, and Re-usable Verification Environments
  • Writing, Modifying, and Maintaining Random and Directed Test Cases and Libraries in SystemVerilog/UVM
  • Writing block level Verilog/System-Verilog directed test-benches and supporting verification team with debug.
  • Analyzing Functional, Code, and Test Plan Coverage
  • Implementing Assertions, Checkers, and Monitors
  • Defining place and route constraints, supporting place-and-route team to debug STA issues.
  • Communicate regularly with other design and verification teams across the corporation.
  • Interact with other groups within the company: Validation, Production, FW, Product Development, Applications.
  • Mentor and coach junior design engineers, if and when required.
  • Occasional travel to Canada to gather project requirements.

This position requires at least BSEE with 8-10 years of SOC/digital/mixed-signal development experience. Candidates are required to have expertise in a wide range of areas in design, tools and flows:

  • BSc/MSc in EE or equivalent with the completion of several complexes ASIC or IC tapeouts in VDSM process technology nodes.
  • Strong working knowledge in one or more of the following disciplines; SystemVerilog, UVM, OVM, VMM.
  • Experience in designing or verifying mixed signal SoC
  • Previous experience in Writing/Implementing/Reviewing Test Plans.
  • Previous experience with SystemVerilog Assertions (SVA), Constrained Random Verification, and Functional coverage.
  • Advantageous to have either design, verification or protocol knowledge of high performance bus protocols such AXI, AHB, and/or DDR.
  • Experience with design tools as nc-sim, simvision & primetime/goldtime, specman.
  • Experience in automation and scriptings such as Python/Perl/TCL/Shell
  • Prior experience on a product that has shipped in significant quantity
  • Experience with all phases of ASIC design (Specification, RTL, verification, synthesis, layout, DFT, etc)
  • Successful track record in project work.
  • Excellent verbal and written communication skills. Strong interpersonal skills.
  • Ability to work efficiently with multi-site teams.
  • Ability to track down bugs and technical problems and work with the design team to ensure timely resolution.
  • Ability to read and understand applicable communication protocol standards.
  • Comfort within the Unix/Linux O/S Environment
  • Exposure to Specman verification language (for legacy projects) [an asset]
  • Experience with DSP design or DSP design implementation [an asset]
  • Experience with designs at 28nm and lower technologies [an asset]
  • Experience with different SERDES protocols including PCIe, SAS/SATA, OTN, Ethernet, etc [an asset]
  • Experience with customer interaction and support experience [an asset]

Equal Opportunity Employer Minorities/Women/Protected Veterans/Disabled